The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a ferroelectric capacitor and fabrication process thereof. Especially, the present invention relates to a ferroelectric memory having improved TDDB resistance and imprint resistance and the fabrication process thereof.
With miniaturization of ferroelectric memory devices, reduction of capacitor area is in progress along with evolution of the ferroelectric circuit used therein from a 2T2C circuit construction to a 1T1C circuit construction. With a 2T2C circuit, two transistors and two capacitors are provided in a single memory cell, while with a 1T1C circuit, only one transistor and only one capacitor are provided in a single memory cell.
In view of the need of securing large switching electric charge for the ferroelectric film, a PZT film is used generally for the ferroelectric film with such reduction of capacitor area and use of the 1T1C circuit construction. Further, along with the reduction of capacitor area and evolution to the 1T1C circuit, there is also a need of suppressing the polarization inversion voltage for the ferroelectric capacitor that uses a PZT film. In relation to this, reduction of PZT film thickness is also in progress.
When the thickness of the PZT film is decreased, on the other hand, there is caused an increase of electric field as long as the same voltage as before is applied thereto, while such increase of electric field leads to increase of leakage current. Such leakage current of ferroelectric capacitor is attributed primarily to the voids existing at the grain boundaries in the ferroelectric film.
In the ordinary process of forming a ferroelectric capacitor having a PZT film, process steps of formation of lower electrode, formation of ferroelectric film, crystallization of the ferroelectric film, formation of upper electrode film, and thermal annealing of the ferroelectric film, are conducted consecutively with this order. With this process, crystals are formed in the ferroelectric film at the time of crystallization of the ferroelectric film, while formation of such crystals leads to formation of voids at the crystal grain boundaries. At the time of formation of the upper electrode film, such voids are filled with material constituting the upper electrode film, while such filling of the voids with the upper electrode film invites decrease of effective film thickness of the ferroelectric film and increase of the leakage current.
Thus, if such voids could be reduced, it becomes possible to decrease the leakage current significantly and it becomes possible to attain low leakage current sufficient for practical use even when the film thickness of the ferroelectric film is reduced.
Thus, Japanese Laid-Open Patent Application No. Hei 10-321809 discloses the following formation method of ferroelectric capacitor.
According to this process, the process of spin-coating, drying and crystallizing of a SrBi2Ta2O9 (SBT) film is repeated three times at first. Next, after fourth spin-coating and drying process, a thermal annealing process is conducted at 600° C. for 5 minutes, and with this, the SBT film is obtained in the form of amorphous phase or microcrystalline phase. Next, formation of the upper electrode film is conducted, followed by a thermal annealing process in a reduced pressure ambient for 30 minutes. According to such a process, it is possible to obtain an SBT film having a smooth top surface.
Further, Japanese Laid-Open Patent Application No. Hei 8-78636 discloses following formation method of a ferroelectric capacitor.
With this method, spin-coating of a (Ba, Sr)TiO3 (BST) film used for the high-K dielectric film and subsequent thermal annealing process thereof at a temperature lower than the crystallization temperature of BST are repeated plural times at first, and formation of upper electrode film is conducted thereafter. Further, thermal annealing process is conducted at a temperature higher than the crystallization temperature of BST.
Further, Japanese Laid-Open Patent Application No. Hei 8-31951 discloses a method of forming, after crystallization of a PZT film, a SrTiO3 (STO) film or BST film thereon in the amorphous state, followed by formation of a Pt upper electrode. Further, Patent Reference 3 discloses the method of crystallizing the STO film or BST film in an oxygen gas ambient immediately after formation thereof.
Further, Japanese Laid-Open Patent Application No. 2001-237384 discloses a method for decreasing the leakage current. According to this prior art, a ferroelectric film of perovskite structure is formed on a lower electrode in a crystalline state, and a precursor liquid of a ferroelectric film is coated upon the foregoing ferroelectric film. After drying, the precursor film is subjected to a low-temperature annealing process conducted at a temperature lower than the perovskite crystallization temperature. After formation of the upper electrode, a high temperature annealing is conducted at a temperature higher than the perovskite crystallization temperature.
Japanese Laid-Open Patent Application No. 2000-40799 discloses a method for forming, in the case of using a Pt film for the upper electrode, forming a layer containing Pb, Pt and O between the ferroelectric film and the upper electrode for the purpose of suppressing hydrogen degradation of the ferroelectric film induced by catalytic action of Pt.
Further, United States Patent Application No. 2005/0161717 describes a method of forming, on a first ferroelectric film of crystalline state, a second ferroelectric film of amorphous state, forming an upper electrode on the second ferroelectric film, and applying, after forming the upper electrode, a thermal annealing process of the ferroelectric film.
Thus, with conventional technologies, it has been not possible to attain, for the ferroelectric capacitor, the goals of: maintaining high switching electric charge; low leakage current; improved insulation breakdown resistance; and improved imprint resistance, at the same time.